In the race to improve transistor performance as well as reduce the size of transistors, transistors have been developed that do not follow the traditional planar format, such that the source/drain regions are located in a fin above the substrate. One such non-planar device is a multiple-gate fin field effect transistor (FinFET). In its simplest form, a multiple-gate FinFET has a gate electrode that straddles across a fin-like silicon body to form a channel region. There are two gates, one on each sidewall of the silicon fin. The source/drain regions are also located in the fin on opposing sides of the channel region.
However, the fabrication of FinFETs can involve cutting the polysilicon line and removing a hard mask layer. The hard mask is used for a first etch process; while cutting the polysilicon line is a second etch process. Removing the hard mask layer after cutting the polysilicon line can lead to rounded polysilicon line edge profiles and rounded contact edge profiles, which in turn can lead to wider than desired process margins. Also, removing the hard mask layer after cutting the polysilicon line can lead to a mushroom defect.
Accordingly, what is needed is a fabrication process for fabricating FinFETs that allows for the removal of a hard mask layer before cutting the polysilicon line to prevent rounded polysilicon line edge profiles, rounded contact edge profiles, wide process margins, and mushroom defects.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.